Struct w806_pac::rcc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub clock_enable: Reg<CLOCK_ENABLE_SPEC>,
    pub adapt_mask: Reg<ADAPT_MASK_SPEC>,
    pub reset_control: Reg<RESET_CONTROL_SPEC>,
    pub clock_divide: Reg<CLOCK_DIVIDE_SPEC>,
    pub debug_control: Reg<DEBUG_CONTROL_SPEC>,
    pub i2s_clock: Reg<I2S_CLOCK_SPEC>,
    pub reset_state: Reg<RESET_STATE_SPEC>,
    /* private fields */
}

Register block

Fields

clock_enable: Reg<CLOCK_ENABLE_SPEC>

0x00 - Software configure clock gate enable

By configuring this clock gating enable register, you can control the clock to shutdown a specified function, so as to achieve the purpose of shutting down a certain module.

In order to provide the firmware with flexibility to control the power consumption of the system, the clock and reset module provides the clock gating function of each module in the system. When the clock of the corresponding module is turned off, the digital logic and clock tree of the module will stop working, which can reduce the dynamic power consumption of the system.

adapt_mask: Reg<ADAPT_MASK_SPEC>

0x04 - Adaptive clock configuration mask

The chip adaptively turns off the clock of some functional modules according to the transition of some internal states.

Please do not change the configuration, otherwise it may cause system abnormality when configuring PMU function.

reset_control: Reg<RESET_CONTROL_SPEC>

0x0c - Software module reset control

The chip provides the soft reset function of each subsystem, and the subsystem reset can be achieved by setting the corresponding bit of this register to 0. However, the reset state will not be automatically cleared. To restore normal operation, the corresponding bit of this register must be set to 1.

The soft reset function does not reset the CPU and watchdog. In this register, the reset operation of APB, BUS1 and BUS2 (corresponding to APB bus, system bus and data bus) is not recommended, which will cause system access device abnormality.

clock_divide: Reg<CLOCK_DIVIDE_SPEC>

0x10 - Software clock division configuration

debug_control: Reg<DEBUG_CONTROL_SPEC>

0x14 - Debug and additional clock control

i2s_clock: Reg<I2S_CLOCK_SPEC>

0x18 - Inter-Integrated Sound clock configuration

reset_state: Reg<RESET_STATE_SPEC>

0x1c - CPU and watchdog reset state register