Struct w806_pac::rcc::clock_enable::W

pub struct W(_);

Register clock_enable writer

Implementations

impl W

pub fn touch(&mut self) -> TOUCH_W<'_>

Bit 21 - Touch sensor module clock gate enable

By default, touch sensor module clock gate is enabled.

pub fn sdio(&mut self) -> SDIO_W<'_>

Bit 18 - Secure digital input/output clock gate enable

By default, SDIO master module clock gate is enabled.

pub fn rsa(&mut self) -> RSA_W<'_>

Bit 16 - RSA Montgomery coprocessor clock gate enable

By default, RSA clock gate is enabled.

pub fn i2s(&mut self) -> I2S_W<'_>

Bit 15 - Inter-Integrated Sound clock gate enable

By default, I2S clock gate is enabled.

pub fn pwm(&mut self) -> PWM_W<'_>

Bit 13 - Pulse-width modulation module clock gate enable

By default, PWM clock gate is enabled.

pub fn adc(&mut self) -> ADC_W<'_>

Bit 12 - Analog-digital converter clock gate enable

pub fn gpio(&mut self) -> GPIO_W<'_>

Bit 11 - General purpose input/output clock gate enable

By default, GPIO clock gate is enabled.

pub fn timer(&mut self) -> TIMER_W<'_>

Bit 10 - Timer module clock gate enable

By default, timer clock gate is enabled.

pub fn dma(&mut self) -> DMA_W<'_>

Bit 8 - Direct memory access clock gate enable

By default, DMA clock gate is enabled.

pub unsafe fn uart<const O: usize>(&mut self) -> UART_W<'_, O>

Universal asynchronous transmitter/receiver enable

By default, UART clock gate is enabled.

pub fn uart0(&mut self) -> UART_W<'_, 1>

Bit 1 - Universal asynchronous transmitter/receiver enable

By default, UART clock gate is enabled.

pub fn uart1(&mut self) -> UART_W<'_, 2>

Bit 2 - Universal asynchronous transmitter/receiver enable

By default, UART clock gate is enabled.

pub fn uart2(&mut self) -> UART_W<'_, 3>

Bit 3 - Universal asynchronous transmitter/receiver enable

By default, UART clock gate is enabled.

pub fn uart3(&mut self) -> UART_W<'_, 4>

Bit 4 - Universal asynchronous transmitter/receiver enable

By default, UART clock gate is enabled.

pub fn uart4(&mut self) -> UART_W<'_, 5>

Bit 5 - Universal asynchronous transmitter/receiver enable

By default, UART clock gate is enabled.

pub fn uart5(&mut self) -> UART_W<'_, 6>

Bit 6 - Universal asynchronous transmitter/receiver enable

By default, UART clock gate is enabled.

pub fn i2c(&mut self) -> I2C_W<'_>

Bit 0 - Inter-Integrated Circuit module enable

By default, I2C clock gate is enabled.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CLOCK_ENABLE_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<CLOCK_ENABLE_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CLOCK_ENABLE_SPEC>> for W

fn from(writer: W<CLOCK_ENABLE_SPEC>) -> Self

Converts to this type from the input type.