Struct w806_pac::rcc::clock_divide::R

pub struct R(_);

Register clock_divide reader

Implementations

impl R

pub fn frequency(&self) -> FREQUENCY_R

Bit 31 - Divide frequency enable

When you need to reconfigure cpu_clk_divider, wlan_clk_divider, bus2_syncdn_factor, sdadc_fdiv, set this register, the hardware will automatically update the above four parameters to the divider, and then clear this register.

pub fn peripheral(&self) -> PERIPHERAL_R

Bits 24:27 - 160-MHz clock divide factor

pub fn bus2_sync(&self) -> BUS2_SYNC_R

Bits 16:23 - Ratio between bus1 and bus2 clock frequency

pub fn wlan(&self) -> WLAN_R

Bits 8:15 - PLL to WLAN system divide factor

After dividing the frequency of the clock from the PLL, it is sent to the wlan system. This register is the frequency division factor, the factor should be >= 2.

pub fn cpu(&self) -> CPU_R

Bits 8:15 - PLL to CPU clock divide factor

Methods from Deref<Target = R<CLOCK_DIVIDE_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CLOCK_DIVIDE_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CLOCK_DIVIDE_SPEC>> for R

fn from(reader: R<CLOCK_DIVIDE_SPEC>) -> Self

Converts to this type from the input type.