Module w806_pac::rcc::clock_divide

Expand description

Software clock division configuration

Structs

Field bus2_sync reader - Ratio between bus1 and bus2 clock frequency

Field bus2_sync writer - Ratio between bus1 and bus2 clock frequency

Software clock division configuration

Field cpu reader - PLL to CPU clock divide factor

Field cpu writer - PLL to CPU clock divide factor

Field frequency reader - Divide frequency enable

Field frequency writer - Divide frequency enable

Field peripheral reader - 160-MHz clock divide factor

Field peripheral writer - 160-MHz clock divide factor

Register clock_divide reader

Register clock_divide writer

Field wlan reader - PLL to WLAN system divide factor

Field wlan writer - PLL to WLAN system divide factor

Divide frequency enable